Video image sequences can be represented using two different techniques: progressive and interlaced techniques. With progressive video, all of the picture elements comprising a frame of a video image are sampled at the same time (where a “frame” refers to one video image snapshot within the sequence of video images). With interlaced video, alternate lines of the video image are sampled at alternate moments in time. Capturing the video image using the interlaced video technique results in the creation of two half-frames, referred to as “fields,” which together constitute a single frame in the video sequence. For instance, note FIG. 1. A first field 102 is commonly referred to as a top field or even field. A second field 104 is commonly referred to as a bottom field or odd field. These two fields (102, 104) together constitute a single frame 106 in a video sequence. Video devices in the United States commonly present video sequences at a frame rate of 29.97 frames per second (that is, roughly 30 frames every second). Televisions and camcorders are common devices that manipulate image sequences using the interlaced technique. Computer monitors and some DVD players are common devices that manipulate image sequences using the progressive technique.
Some applications require that interlaced video image sequences be processed and displayed using a device that is configured to handle only progressive image sequences. These applications therefore require that the image sequence be converted from interlaced format to progressive format. This process is referred to as “de-interlacing.” FIG. 1 illustrates the result of an exemplary de-interlacing process. In this process, the top and bottom fields (102, 104) are reassembled to form a single frame 108 in the video sequence.
A number of techniques exist in the art for de-interlacing video image sequences. However, there is room for improvement in many of these techniques, particularly for those kinds of devices that may be particularly sensitive to variations in bandwidth. More specifically, a technique for de-interlacing video image sequences will inherently require a certain amount of bandwidth as information is transferred to and from memory locations. Modern processors are generally available that can handle such a task in an efficient manner. However, in many competitive marketing environments, the success of a video processing device does not merely depend on the processing power of the device, but also depends on the cost of the device. A developer may therefore choose to forego a certain amount of processing power to provide a less expensive design. It is particularly in these circumstances that the ability to efficiently perform de-interlacing may be jeopardized.
The effectiveness of the de-interlacing operation is particularly brought into question in those cases where less powerful architectures are required to perform other processing tasks in combination with the de-interlacing operation. For instance, modern video processors often require functionality that allows for the rendering of supplemental data along with the sequence of video images. Such supplemental data may comprise close-captioning information, various graphical data associated with the presentation of DVD video sequences, PAL Teletext images, and so on. Such supplemental information is referred to as “video sub-stream” data herein, to distinguish this data from the main sequence of video images (referred to as the “video stream” data herein). It may strain the processing resources of some architectures to handle the combined tasks of de-interlacing and the rendering of video sub-stream data. Similar potential problems may be present with respect to other kinds of resource-intensive processing tasks, such as the display of high definition television (HDTV) signals.
Consider, for example, the case of a device that employs Unified Memory Architecture (UMA). In a UMA design, both the main CPU processor of the device and a graphics processing unit (GPU) share the same memory. (A GPU commonly provides a pipeline for performing a sequence of image rendering tasks, therefore alleviating some of the processing burden that would otherwise be imposed on the CPU). Allocating separate memories to the CPU and GPU will typically result in a more robust processing architecture. However, many developers opt for the UMA architecture so as to provide a less expensive design. This savings in cost can result in a higher bandwidth burden on the device, as both the CPU and GPU are now making demands on the shared memory. It is in these kinds of devices that limitations may arise that prevent video processing operations from becoming too complex. Some UMA-type devices may not be able to efficiently perform de-interlacing and the processing of video sub-stream data at the same time. This can result in the suboptimal display of video data, that is, at less that the normal frame rate. In other cases, these limitations may completely preclude the efficient rendering of video image data.
Accordingly, there is an exemplary need in the art to provide techniques for allowing devices to perform video processing without incurring the above-identified problems. There is a more specific need in the art to provide techniques for robustly handling video processing in bandwidth-challenged devices, such as UMA-type devices.